In a semiconductor memory device, memory cells may be susceptible to errors based on a transient error, soft error or combination. Transient errors may be caused by noise from surrounding components, operating conditions, or operating slightly out of specification. Transient errors may also be caused by defects, part design, or degradation.
For example, memories have been developed that include error detection and/or error correcting codes (ECC) to correct these errors. In a write operation, check data may be written by setting a plurality of sets of 8-bit data to a memory cell array. In a read operation, read data of the plurality of sets are compared with data in a register on the 8-bit unit basis. If there merely is a 1-bit mismatch in the read data, the mismatch may still be detected as an error and the detected one bit error leads to a fail result of the read data in this configuration. Thus, the ECC is effective in detecting a few bit (e.g., 1, 2) errors in the memory cell array, even after a manufacturing and testing process. ECC gives the ability to correct specific bit based defect signatures that are scattered throughout the memory array. This ECC does not work on larger localized defect signatures.
The semiconductor memory device may execute methods to correct defects detected in the memory array. These defects are usually caused by transient errors. For example, memories have been developed that include, redundant rows, redundant columns, and redundant blocks. These redundant elements allow defects not to impact standard operation of the memory device. During testing a defect could cause a bit fail, a single row fail or a single column fail. Once these fails are identified, the address for that fail is stored in a non-volatile memory (e.g. anti-fuses, or other non-volatile memory array). During standard operation the address for the single row or single column fail overrides the internal addressing of the part so the defect is not addressed and the redundant row or column corresponding with the address in the non-volatile array is accessed instead. This effectively corrects the defect. Due to space considerations of the non-volatile array, defects that require multiple redundant rows or redundant columns in a localized area can be addressed by a single block repair. The block repair occupies less space in the non-volatile memory array, but due to the number of redundant physical bits required for the block repair, it is not a very efficient repair.
Thus, the ECC may be effective when the array contains few bit errors, the errors are not detectable at test, or when the errors are generated by transient defects. Standards methods of repair allow for column and row repair when a defect has been identified at test. For larger defects, a block repair would be useful but due to then number of physical bits required is usually inefficient. On dice that are not repairable because of a large defect causing the need for a block repair when there is not one available, the ECC redundant bits could be used as a block repair.